1. Field of the Invention
The present invention relates to a semiconductor device, particularly a semiconductor device including an SOI (Silicon On Insulator) substrate, and to a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2008-026641, filed on Feb. 6, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, semiconductor devices including an SOI substrate have been developed with higher performances. The SOI substrate includes a support substrate, an insulating layer provided on the support substrate, and a semiconductor layer (such as a silicon layer) provided on the insulating layer. A transistor or the like is formed in the semiconductor layer.
Japanese Patent, Laid-open Publication Nos. 2003-68877 and 2005-19453 disclose semiconductor devices using the SOI substrate. Japanese Patent, Laid-open Publication No. 2003-68877 discloses a capacitorless DRAM (Dynamic Random Access Memory) using a floating-gate MOS transistor. Japanese Patent, Laid-open Publication No. 2005-19453 discloses SRAM (Static Random Access Memory) using a fully-depleted MOS transistor.
In the disclosed semiconductor devices, the semiconductor layer included in the SOI substrate has two regions of different thicknesses (thin film region and thick film region) to achieve desired electronic characteristics. A memory cell is mainly formed in the thin film region, and a peripheral circuit for inputting and outputting data to the memory cell is mainly formed in the thick film region.
In the conventional semiconductor devices each including the SOI substrate, the following problems arise when element isolation regions of an STI (Shallow Trench Isolation) structure is formed in the semiconductor layer including the two regions of different thicknesses.
FIG. 22A is a cross-sectional view illustrating a conventional semiconductor device 220 when STI-type isolation regions are formed. The semiconductor device 220 includes an SOI substrate 200 including a support substrate 201, an insulating film 202 provided on the support substrate 201, and a semiconductor layer 203 provided on the insulating film 202. The semiconductor layer 203 includes a thin region A and a thick region B. For convenience, the semiconductor layer 203 in the region A is denoted as a semiconductor layer 203a, and the semiconductor layer 203 in the region B is denoted as a semiconductor layer 203b. 
In the semiconductor device 220, thicknesses of the SOI substrate (from the rear surface of the support substrate to the upper surface of the semiconductor layer) in the regions A and B are Da and Db, respectively. STI-type isolation regions 204a and 204b made of insulating films are formed in the semiconductor layers 203a and 203b. In the region B, the semiconductor layer 203b is thicker than the STI-type isolation regions 204b, and therefore the bottom surfaces of the STI-type isolation regions 204b are not in contact with the insulating layer 202. Thereby, a potential of the semiconductor layer 203b can easily be fixed by a given voltage being applied to the semiconductor layer 203b. 
To form the semiconductor device 220 as shown in FIG. 22A, the SOI substrate 200 including the semiconductor layer 203 including the two regions of different thicknesses is prepared by a known method disclosed in, for example, Japanese Patent, Laid-open Publication No. 2005-19453. Then, a photoresist film 208 is formed on the semiconductor layer 203, a resist pattern is formed by exposing the photoresist film 208, and then the STI-type isolation regions 204 (204a and 204b) are collectively formed in the regions A and B.
With the further miniaturization of semiconductor devices, a higher resolution is required for a stepper (exposure apparatus) used for manufacturing semiconductor devices. To achieve a high resolution, a light source of a short wavelength and a large aperture lens are used in the stepper, and a focal depth is shallow. Thereby, planarization of a surface targeted for lithography is important in a lithography process using a stepper of high resolution.
However, the SOI substrate 200 has two different thicknesses Da and Db, and thereby a step occurs on a surface of the photoresist film 208, causing misalignment of focuses upon the STI-type isolation regions 204a and 204b in the regions A and B being simultaneously exposed. As a result, it is difficult to simultaneously form desired patterns in the regions A and B. In other words, it is difficult to simultaneously form the microscopic STI-type isolation regions 204 in the semiconductor layer 203 including the regions of different thicknesses with the photoresist 208 as a mask. The further semiconductor devices are miniaturized, the further misalignment of focuses upon lithography affects a pattern formation.
It can be considered to separately form the STI-type isolation regions 204a and 204b in the regions A and B. In this case, however, the following problems arise.
FIG. 23 is a cross-sectional view schematically illustrating a semiconductor device in which an insulating film is formed in the thin film region A after the STI-type isolation regions are formed in the thick film region B. The STI-type isolation regions are generally formed by providing recesses in the semiconductor layer, embedding insulators therein, and planarizing the surface thereof. Hereinafter, problems in this case are explained.
In a method of manufacturing a semiconductor device 230 as shown in FIG. 23, STI-type isolation regions 204b are formed only in the region B, followed by forming a silicon oxide film (SiO2) 205 and a silicon nitride film (Si3N4) 206 on the entire surface of the semiconductor layer 203 (203a and 203b) included in the SOI substrate 200. Then, the silicon oxide film 205 and the silicon nitride film 206 at portions that will be STI-type isolation regions in the region A are etched with a photoresist film (not shown) as a mask to form openings. At this time, misalignment of focuses does not occur since exposure of the photoresist film is performed only in the region A. Then, the semiconductor layer 203a in the openings is removed to form the openings 209. Lastly, an insulating film 207, such as a silicon nitride film, is formed on the silicon nitride film 206 and fills up the openings 209, and thereby the semiconductor device 230 is formed.
The insulating film 207, the silicon nitride film 206, and the silicon oxide film 205 that remain on the SOI substrate 200 are removed in the subsequent processes, and thereby the semiconductor device 220 as shown in FIG. 22A is formed. At this time, the remaining films on the SOI substrate 200 are removed by the surface of the SOI substrate 200 being planarized by CMP (Chemical Mechanical Polishing).
However, the SOI substrate 200 has different thicknesses in the regions A and B, and therefore there is a step on the surface targeted for CMP. Accordingly, it is difficult to planarize the entire surface of the semiconductor device 230 by CMP except for when the total area of the regions A and B is extremely smaller than that of the entire SOI substrate 200. When capacitorless DRAM is formed, for example, the total area ratio of the regions A and B is approximately 6:4, and multiple regions A and B are mixed. Thereby, film thicknesses after CMP (from the rear surface of the SOI substrate to the uppermost surface) cannot be uniformed even if the surface of the semiconductor device 230 is planarized by CMP, causing fluctuation in film thicknesses due to steps among adjacent regions. Therefore, it has been difficult to uniformly form the STI-type isolation regions 204a and 204b in the SOI substrate 200, preventing progress of miniaturization. In other words, it has been difficult to separately form, by CMP, the microscopic STI-type isolation regions 204a and 204b in the SOI substrate 200 including the semiconductor layer 203 including the regions of different thicknesses.
To separately form the STI-type isolation regions 204a and 204b in the regions A and B, alignment has been problematic upon exposure of a photoresist film for forming the STI-type isolation regions 204a. In other words, alignment of a pattern of the STI-type isolation regions 204a is preferably carried out with the position of a pattern of the previously-formed STI-type isolation regions 204b as a reference so that relative positions between the STI-type isolation regions 204a and 204b are maintained.
If the photoresist film for forming the STI-type isolation regions 204a in the region A is formed (exposed) with the position of the pattern of the STI-type isolation regions 204b in the region B as a reference, the upper surfaces of the STI-type isolation regions 204b and the semiconductor layer 203b are substantially equal since the STI-type isolation regions 204b have already been formed. Additionally, the silicon oxide film 205, the silicon nitride film 206, and the photoresist film (not shown) are deposited on the STI-type isolation regions 204b when the photoresist is exposed.
As a result, there has been need to detect the position of alignment marks formed using the pattern of the STI-type isolation regions 204b through the multiple deposited films upon the alignment of a pattern of the STI-type isolation regions 204a. However, it has been difficult to precisely detect the positions of the alignment marks since multiple films have been deposited on the alignment marks and there are few steps on the upper surface of the semiconductor layer 203b. Therefore, misalignment is likely to occur, which has been one of factors preventing miniaturization of semiconductor devices.